1. Field of the Invention
The present invention relates to solid-state image pickup devices. In particular, the present invention relates to a solid-state image pickup device such as a CMOS (complementary metal oxide semiconductor) image sensor having pixels each including a conversion unit converting charge generated by a photoelectric conversion unit into pixel signals. Such a CMOS image sensor is produced by applying or appropriately employing a CMOS process.
The solid-state image pickup device can be an element type formed as one chip or be composed of a plurality of chips.
2. Description of the Related Art
CMOS image sensors have a plurality of pixels arranged two-dimensionally, each including a photoelectric conversion unit and a plurality of MOS transistors. The CMOS image sensors convert charge generated by the photoelectric conversion unit into pixel signals and read out the pixel signals. Recently, attention has been focused on such CMOS image sensors as image pickup elements applied to devices such as cameras in mobile phones, digital still cameras, and digital video cameras.
Referring to FIG. 22, an example of a configuration of a CMOS image sensor (equivalent circuit) is illustrated. A CMOS image sensor 1 includes an image pickup area 4 having a plurality of pixels 3 arranged two-dimensionally on a semiconductor substrate. Each of the pixels 3 includes a photoelectric conversion unit, i.e., a photodiode 2 for performing photoelectric conversion, and a plurality of MOS transistors for selectively reading out a signal from the photodiode 2. In addition, the CMOS image sensor 1 is provided with peripheral circuits for selecting the pixels and outputting signals. The peripheral circuits are arranged around the image pickup area 4 on the semiconductor substrate. In this example, the MOS transistors of each of the pixels 3 in the image pickup area 4 include a transfer transistor 8, a reset transistor 9, and an amplifying transistor 10. The peripheral circuits include a circuit for selecting pixels (vertical scanning circuit) 5 and an output circuit (horizontal scanning/outputting circuit) 6 which are formed using CMOS transistors.
In FIG. 22, for each of the pixels 3, the photodiode 2 is connected to the source of the transfer transistor 8. A transfer line 11 is connected to the gate of the transfer transistor 8. The drain of the transfer transistor 8 is connected to the source of the reset transistor 9. A so-called floating diffusion provided between the drain of the transfer transistor 8 and the source of the reset transistor 9 is connected to the gate of the amplifying transistor 10. The gate of the reset transistor 9 is connected to a reset line 12. In addition, a power source line 13 for supplying electric power is connected to the drain of the reset transistor 9 and the drain of the amplifying transistor 10. The source of the amplifying transistor 10 is connected to a vertical signal line 14.
In this CMOS image sensor 1, for each of the pixels 3, photoelectric conversion is performed by the photodiode 2. The transfer transistor 8 transfers photoelectrons (signal charge) in the photodiode 2 to the floating diffusion FD. Since the floating diffusion FD is connected to the amplifying transistor 10, a signal corresponding to the potential of the floating diffusion FD is output through the amplifying transistor 10 to the vertical signal line 14.
As an example of a layout of the pixels 3, Japanese Unexamined Patent Application Publication No. 2003-007995 discloses a layout in which a pixel group is arranged so as to be shifted in the horizontal and vertical directions by one-half of a predetermined pitch with respect to another pixel group so as to form a diagonal grid, as illustrated in FIG. 23. With a CMOS image sensor having this diagonal pixel array and signal processing, the number of recording pixels exceeds the number of effective pixels, which permits an increase in resolution.
As illustrated in FIG. 23, in a CMOS sensor with such a diagonal pixel array, individual wires are normally arranged in the vertical and horizontal directions with respect to the chip and image-pickup area, as in other types of sensor. For example, the CMOS sensor has a multilayer wiring structure constituted by a first layer of vertical wiring, a second layer of horizontal wiring, and a third layer of wiring used as power source wiring and also as a light shield. FIG. 23 illustrates only vertical lines 16 and 17 disposed on the first layer.
On the other hand, Japanese Unexamined Patent Application Publication No. 2000-101061 discloses a frame transfer CCD image sensor in which combinations of metal or metal silicide auxiliary electrodes are disposed at equal intervals so as to be diagonally oriented with respect to transfer electrodes formed of polycrystalline silicon. This configuration is proposed with a view to minimizing the area covered by the light shielding auxiliary electrodes in a light receiving portion, and thus realizing both efficient light reception/image-pickup and high-speed, highly efficient charge transfer with supply of transfer voltage to the transfer electrodes.